发明名称 |
Integration of the borderless contact salicide process |
摘要 |
A method for integrating salicide and borderless contact processes while avoiding current leakage at the shallow trench isolation edge is described. Shallow trench isolation (STI) regions are formed in a semiconductor substrate electrically isolating an active area from other active areas. A gate electrode and associated source and drain regions are formed in the active area wherein dielectric spacers are formed on sidewalls of the gate electrode. A metal layer is deposited over the gate electrode and associated source and drain regions. A first annealing of the semiconductor substrate transforms the metal layer into a metal silicide layer over the gate electrode and source and drain regions. The metal layer which is not transformed into a metal silicide overlying the dielectric spacers and shallow trench isolation regions is removed. An etch stop layer is deposited over the surface of the semiconductor substrate. A second annealing changes the metal silicide layer to a phase having lower resistance and also densifies the etch stop layer. An interlevel dielectric layer is deposited over the densified etch stop layer. A borderless contact opening is formed through the interlevel dielectric layer and the etch stop layer to one of the source and drain regions and the contact opening is filled with a conducting layer to complete fabrication of the integrated circuit device.
|
申请公布号 |
US6265271(B1) |
申请公布日期 |
2001.07.24 |
申请号 |
US20000489967 |
申请日期 |
2000.01.24 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY |
发明人 |
THEI KONG-BENG;WUU SHOU-GWO |
分类号 |
H01L21/285;H01L21/336;(IPC1-7):H01L21/336;H01L21/44 |
主分类号 |
H01L21/285 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|