| 发明名称 |
Laterally situated stress/strain relieving lead for a semiconductor chip package |
| 摘要 |
A semiconductor chip package having an internal laterally curved lead in order to compensate for the CTE mismatch between a semiconductor chip and a supporting substrate, such as a PWB.
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| 申请公布号 |
US6265759(B1) |
申请公布日期 |
2001.07.24 |
| 申请号 |
US19980120006 |
申请日期 |
1998.07.21 |
| 申请人 |
TESSERA, INC. |
发明人 |
DISTEFANO THOMAS H.;FJELSTAD JOSEPH;SMITH JOHN W. |
| 分类号 |
H01L23/13;H01L23/31;H01L23/498;(IPC1-7):H01L23/495;H01L23/48 |
主分类号 |
H01L23/13 |
| 代理机构 |
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代理人 |
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| 主权项 |
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