| 摘要 |
The present invention provides a semiconductor memory device has an input first stage circuit for receiving an external input of a clock signal, an output circuit connected to the input first stage circuit for receiving an output signal from the input first stage circuit so that the output circuit outputs data on the basis of the output signal, a delay device connected to the input first-stage circuit for delaying the output signal from the input first-stage circuit in order for synchronizing in timing between the data from the output circuit and the lock signal, wherein the delay device further comprises an output delay circuit having a circuit configuration substantially identical with or equivalent to a circuit configuration of the output circuit, and an input delay circuit being connected to the output delay circuit and the input delay circuit having a circuit configuration substantially identical with or equivalent to a circuit configuration of the input first-stage circuit.
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