| 摘要 |
A semiconductor wafer comprises a silicon substrate, and a dielectric layer. A gate is formed on the dielectric layer. A first silicon oxide layer is uniformly formed on the semiconductor wafer. A first ion implantation process is performed to form two doped areas on the silicon substrate that are used as two lightly doped drains of a MOS transistor. A second silicon oxide layer is formed on the semiconductor wafer. A sacrificial layer is formed on the second silicon oxide layer. A first etching process is performed to remove the sacrificial layer on top of the gate, causing the gate to protrude from the remaining sacrificial layer for a predetermined height. A second etching process is performed to remove the first and second silicon oxide layers on the protruding portion of the gate. After removing the sacrificial layer completely, a silicon nitride layer is uniformly formed on the semiconductor wafer. A third etching process is performed to vertically remove the silicon nitride layer on top of the gate, thereby forming a spacer. Finally, a second ion implantation process is performed to form two doped areas on the silicon substrate, which are used as source and drain of the MOS transistor.
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