| 摘要 |
An apparatus is described for controlling data transfer operations between a main memory and other devices in a computer system. A memory controller receives data transfer request signals and associated latency identification values, each corresponding with a maximum time interval in which to service the respective data transfer requests. The latency identification values are periodically modified and compared to indicate the current highest priority request. In the event that service of a particular requested data transfer operation must be provided imminently, priority override circuitry is provided. In this way, those devices having particular latency requirements can be provided with timely access to the main memory, and need not have separately dedicated memory or buffers.
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