发明名称 |
Wafer burn-in test circuit and method for testing a semiconductor memory device |
摘要 |
A wafer burn-in test circuit of a semiconductor memory device having a plurality of memory cells arranged in a row/column matrix, is provided, including:a sub word line driver connected to first and second word line groups each connected to true cells and complement cells forming the memory cells, and responding to a predecoded low address; and first and second power lines respectively supplying power to the corresponding first and second power line groups by a switching operation of the sub word line driver, wherein a ground power source is applied to the first and second power lines during a normal operation, and the ground power source and a step-up power source are alternately applied to the first and second power lines during a wafer burn-in test operation.
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申请公布号 |
US6266286(B1) |
申请公布日期 |
2001.07.24 |
申请号 |
US19990457909 |
申请日期 |
1999.12.08 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
CHO SOO-IN;CHOI JONG-HYUN |
分类号 |
G01R31/26;G01R31/28;G11C7/00;G11C11/401;G11C11/407;G11C29/00;G11C29/02;G11C29/06;G11C29/50;H01L21/66;H01L21/8242;H01L27/108;(IPC1-7):G11C7/00 |
主分类号 |
G01R31/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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