发明名称 |
WAFER LEVEL PACKAGE |
摘要 |
PURPOSE: A wafer level package is provided to reduce a pitch between external connection terminals by using a conductive pillar instead of an existing solder ball. CONSTITUTION: A bond pad(11) is formed on a surface of a semiconductor chip. A pattern film is adhered on a surface of the semiconductor chip in order to expose the bond pad(11). A metal pattern(23) is arranged on a surface of the pattern film. A metal wire(30) connects one part of the metal pattern(23) of the pattern film with the bond pad(11). An encapsulant(40) encapsulates a wire bonding region corresponding to the metal wire(30). A conductive pillar(50) is formed on the other part of the metal pattern(23) of the pattern film.
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申请公布号 |
KR20010068590(A) |
申请公布日期 |
2001.07.23 |
申请号 |
KR20000000583 |
申请日期 |
2000.01.07 |
申请人 |
CHIPPAC KOREA CO., LTD. |
发明人 |
KIM, YEONG SIL;RYU, GI TAE;YOO, SEONG SU;YOON, HAN SIN |
分类号 |
H01L21/60;(IPC1-7):H01L21/60 |
主分类号 |
H01L21/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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