| 摘要 |
A frequency multiplier is provided that increases operational stability by using a Delay Locked Loop (DLL). The frequency multiplier includes a phase detector for detecting a phase difference between an input signal and a feed-back signal, a loop filter for outputting a control signal based on the phase difference detected by the phase detector and a voltage-controlled delay unit for varying a delay ratio of the input signal and outputting divided signals in accordance with the control signal from the loop filter. A first SR flip-flop receives a pair of earlier output signals that are divided into 1/4 and 2/4 period signals from the voltage-controlled delay unit and outputs a first duty cycle signal. A second SR flip-flop receives a pair of later output signals that are divided into 3/4 and 4/4 period signals from the voltage-controlled delay unit and outputs a second duty signal. A logic circuit such as an OR-gate receives the outputs from the first and second SR flip-flops and outputs a signal having a predetermined duty cycle, for example, a 50% duty cycle. The frequency multiplier further has reduced size and power requirements. |
