| 摘要 |
PROBLEM TO BE SOLVED: To obtain a stable internal clock signal generating circuit capable of suppressing oscillation to be generated due to fluctuation of a power source, etc. SOLUTION: This internal clock signal generating circuit is constituted so that results of (n+1) times of comparison in the past between two values whether a phase is advanced or delayed by a phase comparator circuit 13 are stored in a shift register 14, the higher result among the results of the (n+1) times of comparison is outputted to a variable phase circuit 12 as a phase control signal by a phase control circuit 15 and the variable phase circuit 12 performs phase adjustment of an internal clock signal intclk based on the inputted phase control signal. |
