发明名称 LOGIC VERIFICATION SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide an ideal logic verification system which is applied to the large scale logic of data communication equipment, etc., and by which the number of prepared test data strings is reduced and the result can be easily verified. SOLUTION: A logic operation model A102 recognizes a test data storing 101 of a byte format, prepared on the basis of test items by a parameter 103 defining an input output file name, fetches the test data string 101 in a data transmission part 104, converts the fetched test data string into waveform data and gives the wave form to object logic 105 to be verified as a signal value. The logic 105 performs a logic operation, on the basis of the given signal value and outputs to an outputs port the signal change information. The outputted signals change information is fetched by the data receiving part 107' of a logic operation model B 106, once stored in a buffer 109' for a loop with bit string data as they are and also outputted to a result log file B108 and a new test data string file B110 as data of byte format. The data stored in the buffer 109' are given to the logic 105 as waveform data.
申请公布号 JP2001195440(A) 申请公布日期 2001.07.19
申请号 JP20000004677 申请日期 2000.01.13
申请人 HITACHI LTD 发明人 TANIGUCHI MITSURU;MIZOGAMI YOSHITO
分类号 G01R31/28;G06F11/22;G06F17/50;H04L29/14 主分类号 G01R31/28
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