| 摘要 |
<p>A filtering and synchronization circuit synchronizes an asynchronous input signal to a clock signal and generates a synchronous output signal. The circuit synchronizes both the leading edge and the trailing edge of the input signal and also blocks or filters out oscillations in the input signal for a period following the edges. The circuit includes an input signal latch which receives the input signal and provides a latched signal which does not change state even if the input signal subsequently changes state until the latched signal is synchronized to the clock signal. The circuit further includes a synchronizer which synchronizes the latched signal with the clock signal. The synchronizer provides feedback signals to the input signal latch to permit the input signal latch to recognize a change in the state of the input signal only after the synchronizer has synchronized the previous state of the input signal. The feedback signals can be selectively delayed to extend the time during which the input signal latch does not recognize changes in the state of the input signal.</p> |
