| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory in which an input of high speed packet data is provided and the confirmation of operation can be performed by a low speed tester. SOLUTION: A semiconductor memory 1 generates a high speed internal clock by a DLL circuit 16 based on a clock signal inputted from a tester in a test mode. An internal clock is given to serial/parallel conversion circuits 18, 20 serial/parallel-converting data given by a packet form and an interface circuit 22 decoding an output of the serial/parallel conversion circuits 18, 20 and outputting commands of ACT and the like to a DRAM core 26. Also, an internal packet generating circuit generates a packet signal for test at high speed by an internal clock. Therefore, the confirmation of operation can be performed without inputting externally a packet signal. |
