| 摘要 |
PROBLEM TO BE SOLVED: To provide an electronic system provided with an instruction programmable processor like a digital signal processor provided with a primary program cache memory and an instruction buffer sub system 40. SOLUTION: The sub system 40 is provided with a program data RAM 60 for which a tag RAM 54 and a tag comparator 52 are combined and a loop cache sub system 62 parallel to the RAM 60. An instruction fetch unit 10 supplies a fetch address to the tag comparator 52 and the sub system 62. The sub system 62 is provided with a branch cache register file 76 for storing an instruction OP code corresponding to the sequence of the fetch address starting from a reference address. |
