CLOCK CONTROL CIRCUIT FOR RAM BUS DRAM

摘要

PROBLEM TO BE SOLVED: To provide a clock control circuit of low consumption power by judging previously whether an applied instruction for a RAM bus DRAM is READ or current control or not and enabling a clock signal outputting internal data to the outside by only the instruction. SOLUTION: This circuit comprises an input signal detecting means 100 generating an enable-signal when one signal out of first compared signals by an address value to be selected and a device address DA value and second compared signals by an address value to be selected and a COLX packet DA value is activated and an instruction is READ (R) or current control CC, a signal generating means 400 generating a clock enable-signal when one signal out of the first and the second compared signals is activated, an output signal holding means 200 controlling so that a clock enable-signal is held at the time or R or CC instruction, and an output signal control means 300 controlling generation of a clock enable signal when an instruction is not R or CC instruction.