| 摘要 |
PROBLEM TO BE SOLVED: To provide a sample-and-hold circuit that can reduce leakage of a switch signal to an output signal from gates of MOS analog switches. SOLUTION: The sample-and-hold circuit is provided with a 1st analog switch 3 with a gate 8 consisting of a signal input line 1, a signal output line 2 and an N-channel MOS transistor(TR) where a parasitic capacitance 6 is in existence between the 1st analog switch 3 and the signal output line 2, with a 2nd analog switch 4 with a gate 9 consisting of an N-channel MOS TR where a parasitic capacitance 6 is in existence between the 2nd analog witch 4 and the signal output line 2, with a capacitance 7 connected between a signal output line 2 and a reference level (VSS), with a switch signal generating circuit 10 that generates a 1st switch signalΦ1 and with a delay circuit 11 that delays the 1st switch signalΦ1 by a prescribed time and generates a 2nd switch signalΦ2.
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