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经营范围
发明名称
Circuit synthesis and verification using relative timing
摘要
申请公布号
GB0112696(D0)
申请公布日期
2001.07.18
申请号
GB20010012696
申请日期
1999.11.02
申请人
INTEL CORPORATION
发明人
分类号
G06F17/50
主分类号
G06F17/50
代理机构
代理人
主权项
地址
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