| 摘要 |
A memory cache sequencer circuit manages the operation of a memory cache and cache buffer so as to efficiently forward memory contents being delivered to the memory cache via the cache buffer, to a multithreading processor awaiting return of those memory contents. The sequencer circuit predicts the location of the memory contents that the processor is awaiting, and speculatively forwards memory contents from either the cache buffer or memory cache, while simultaneously verifying that the speculatively forwarded memory contents were correctly forwarded. If the memory contents were incorrectly forwarded, the sequencer circuit issues a signal to the processor receiving the speculatively forwarded memory contents to ignore the forwarded memory contents. This speculative forwarding process may be performed, for example, when a memory access request is received from the processor, or whenever memory contents are delivered to the cache buffer after a cache miss. The sequencer circuit includes a plurality of sequencers, each storing information for managing the return of data in response to one of the potentially multiple misses and resulting cache linefills which can be generated by the multiple threads being executed by the processor. For each thread, there is one designated sequencer, which is managing the most recent cache miss for that thread; the information stored by the designated sequencer is used to predict the location of data for speculative forwarding, subject to subsequent verification based on the information in other sequencers and the cache directory.
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