发明名称 Method for fabricating a salicide gate
摘要 A method of fabricating a salicide gate is provided, wherein a logic region and a memory cell region are formed on a substrate. A plurality of polysilicon gates and adjoining source/drain regions are also formed in both regions. A protection layer is formed to cover the polysilicon gates and the source/drain regions, followed by forming a photoresist layer on the substrate. A blanket defocus exposure is then conducted, whereby a part of the protection layer on the top surface of the polysilicon gates in both regions is eventually removed. Another photoresist layer is formed in the memory cell region, while the protection layer in the logic region is removed. A self-aligned silicide process is then conducted to form the salicide gates in both regions, and to selectively forming salicide layers on the source/drain regions in the logic region only.
申请公布号 US6261898(B1) 申请公布日期 2001.07.17
申请号 US20000654008 申请日期 2000.09.01
申请人 UNITED MICROELECTRONICS CORP. 发明人 WU DER-YUAN
分类号 H01L21/8234;H01L21/8242;(IPC1-7):H01L21/824 主分类号 H01L21/8234
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