| 摘要 |
A semiconductor memory device for improving the transmission data rate of a data input and output bus, and a memory module including the same, are provided. The memory module includes a plurality of clock synchronous memory devices that share a single data bus line. More specifically, the memory module includes a printed circuit board having an electrical connector including the data bus line, a first set of synchronous memory devices arrayed on the printed circuit board, a second set of synchronous memory devices arrayed on the print circuit board, and a clock signal generator electrically connected to the first and second set of synchronous memory devices. The clock signal generator operates to receive a clock signal from the electrical connector and to generate a first clock signal that is matched with the received clock signal and a second clock signal that is delayed with respect to the received clock signal for half the period of the received clock signal. In the memory module, memory data in the first set and memory data in the second set are alternately output to the data bus line.
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