Ferroelectric memory device

摘要

Disclosed is a ferroelectric memory device having a memory cell structure where a plurality of ferroelectric capacitor are connected to one switching transistor, and a plurality of data are outputted according to one address input. The ferroelectric memory device comprises a plurality of word lines for driving a corresponding memory cell in accordance with an input address; a plurality of bit lines crossing said word lines, respectively; a plurality of switching transistors connected both to the bit lines and the word lines, respectively; and a plurality of dielectric capacitors wherein one end is coupled in common to a node of the switching transistor, respectively; wherein a plurality of output data are outputted by selecting a memory cell including at least one switching transistor corresponding to the plurality of switching transistors, and to the plurality of dielectric capacitors.