| 摘要 |
The present invention is directed to a method of forming a transistor having very shallow junctions and a reduced channel length, and a transistor incorporating same. In general, the method comprises forming a first process layer above a semiconducting substrate, and forming a second process layer comprised of an oxidation resistant material above the first process layer. The method continues with the formation of an opening in the first and second process layers and oxidation of the substrate lying within the opening to form a third process layer. Next, a second opening is formed in the third process layer, and a plurality of sidewall spacers are formed in the second opening. The method concludes with the formation of a gate dielectric above the substrate and between the sidewall spacers, the formation of a gate conductor above the gate dielectric, and the formation of a plurality of source and drain regions in the substrate. The transistor is comprised of a recess formed in the substrate, a gate dielectric positioned above the substrate lying within the recess, the interface between said gate dielectric and said substrate being positioned beneath the surface of said substrate. The transistor further comprises a gate conductor positioned above the gate dielectric, a plurality of sidewall spacers positioned adjacent the gate conductor, and a plurality of source/drain regions formed in the substrate.
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