发明名称 Variable rate MPEG-2 video syntax processor
摘要 An MPEG-2 video signal decoder includes a syntax parser which is implemented as a state machine. The state machine defines a plurality of states in which discrete parsing operations are performed to decode the MPEG-2 bit-stream. A distinct processing time is established for each state in the state machine. Even if the processing for a particular state is complete before the end of the respective processing time for the state, the transition from the state to the next state does not occur until the end of the time interval. The processing time for each state is set by a microprocessor coupled to the state machine. The processing time for each state may be changed based on image content or to accommodate changes in the circuitry used to implement the state machine. The processing times for the states may also be adjusted to accommodate changes in other processing elements, separate from the state machine but which depend on the state machine for the processing that they perform. One way in which the processing times may be changed is to conform the processing of an image or a sequence of images to a predetermined maximum time interval.
申请公布号 US6263019(B1) 申请公布日期 2001.07.17
申请号 US19980169580 申请日期 1998.10.09
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 RYAN ROBERT T.
分类号 H04N5/92;G06T9/00;H04N7/24;H04N7/26;H04N7/30;H04N7/32;H04N7/50;(IPC1-7):H04B1/66 主分类号 H04N5/92
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