Level shifting CMOS I/O buffer

摘要

A low power CMOS bidirectional I/O buffer that translates low voltage core logic level signals into the higher voltage logic level signals. A first predrive stage is provided, comprising buffers (e.g., CMOS inverters) for tuning and balancing the circuit and the core signal combining circuit of a second predrive stage, thereby enabling IC designers to reduce the size of transistors in the level-shifting stage and providing more flexibility in the tuning of the predrive circuitry to synchronize or balance the logical transitions of the complementary transistors of the output driving stage. The invention provides a faster balanced level-shifting output buffer which enables higher frequency operation.