发明名称 Dual cache with multiple interconnection operation
摘要 A computer system having cache modules interconnected in series includes a first and a second cache module directly coupled to an address generating line for parallel lookup of data and data conversion logic coupled between the first cache module and said second cache module.
申请公布号 AU1470301(A) 申请公布日期 2001.07.16
申请号 AU20010014703 申请日期 2000.11.07
申请人 INTEL CORPORATION 发明人 ZEEV SPERBER;JACK D. DOWECK;NICOLAS KACEVAS;ROY NESHER
分类号 G06F12/08 主分类号 G06F12/08
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