MULTIPLE ARBITER JITTER ESTIMATION SYSTEM AND RELATED TECHNIQUES

摘要

A digital circuit includes a plurality of arbiters, each arbiter having first and second input ports and an output port at which is provided an arbiter output signal. Each first input of the plurality of arbiters is connected to a first common line and each second input of the plurality of arbiters is connected to a second common line. The digital circuit further includes a decision circuit, having a plurality of inputs and an output, with each of the inputs of the decision circuit coupled to a corresponding one of the output of the plurality of arbiters. The decision circuit provides an output signal indicative of the time difference between a signal fed to the first common line and a signal fed to the second common line. With such an arrangement, phase jitter or timing jitter in a clock network can be measured with relatively high resolution and the system cam resolve cycle-by-cycle jitter with a predetermined resolution.