| 摘要 |
<p>A parallel processing system composed of a regular array of programmable logic devices (461), each of which can be configured to perform any logical mapping from inputs to outputs. The configuration of each device is specified by a small program memory (200) contained inside each device. Any device's program memory can be read or written by any other device connected to it within the array. This facilitates the development of extremely parallel systems whose component devices can be modified in parallel. The resulting system is thus completely self-reconfigurable, avoiding the bottlenecks and critical failure points found in inherently externally-configured systems. This system's programmable devices utilize a non-shifting memory (200) for storing their programs. This results in a significant reduction in the size and complexity of each programmable device as compared to a shift register-based design. Additionally, this leads to more predictable behavior as compared to a shift register-based design if only part of a cell's memory is read or written.</p> |
