发明名称 |
Semiconductor device |
摘要 |
The column address strobe signal (CAS) which is changed in cycles as many as a plurality of times of a clock signal cycle is input to the memory block (MBK0 to MBKn). A plurality of serial data readout from the memory cell array (10) and parallel/serial converted by a parallel/serial converter circuit (21) in synchronous with a clock signal cycle are output for every cycle when the column address signal (CASADR) is changed. Parallel data input to the memory block and serial/parallel converted by a serial/parallel converter circuit (25) in synchronous with the clock signal cycle are written in the memory cell array. In this way, the access specification that the column address strobe signal is varied once per n cycles of the clock signal allows more rapid memory operation.
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申请公布号 |
US2001007539(A1) |
申请公布日期 |
2001.07.12 |
申请号 |
US20010756800 |
申请日期 |
2001.01.10 |
申请人 |
TANAKA YOUSUKE;KATAYAMA MASAHIRO;YOKOYAMA YUJI;AKASAKI HIROSHI;MIYAOKA SHUICHI;KOBAYASHI TORU |
发明人 |
TANAKA YOUSUKE;KATAYAMA MASAHIRO;YOKOYAMA YUJI;AKASAKI HIROSHI;MIYAOKA SHUICHI;KOBAYASHI TORU |
分类号 |
G11C11/407;G06F1/06;G11C7/10;G11C8/18;G11C11/401;G11C11/409;G11C11/4096;H04L7/00;(IPC1-7):G11C5/00;G11C7/00;G11C29/00;G11C8/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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