发明名称 |
Frequency detector and phase-locked loop circuit including the detector |
摘要 |
<p>A three-state phase detector, including two latches and one NAND gate, is provided with two additional latches. To detect a phase difference between first and second input clock signals R and V, the phase detector alternates among three states responsive to a rising edge of the input R or V signal. Each of the two additional latches and an associated latch in the phase detector together constitute one shift register. When the phase detector gets back to its neutral state, the NAND gate generates a reset signal, thereby resetting all of these four latches. Two isolated pulse generators are further provided. Each of the pulse generators makes the pulse width of a frequency difference pulse signal, output from associated one of the additional latches, constant and then outputs the pulse signal with the constant width. <IMAGE></p> |
申请公布号 |
EP1115198(A2) |
申请公布日期 |
2001.07.11 |
申请号 |
EP20000128707 |
申请日期 |
2000.12.29 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
DOSHO, SHIRO;YANAGISAWA, NAOSHI;TOYAMA, MASAOMI |
分类号 |
H03D13/00;H03K5/26;H03L7/087;H03L7/089;H03L7/113;H03L7/18;(IPC1-7):H03D13/00 |
主分类号 |
H03D13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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