Output stage for an array of electrical transducers

摘要

An output stage for an array of transducer elements, comprising a plurality of first stage amplifiers connected to the array and a plurality of second stage amplifiers connected to the first stage amplifiers by way of a plurality of data bus lines, thus forming a two stage pipeline architecture in the analog output path which maintains fast pixel rates with minimal ADC (analog digital converter) arrangement. A novel power supply and the use of differential amplifiers in connection with a black signal level as a reference voltage are also described.