发明名称 SELF-TEST CIRCUIT AND MEMORY DEVICE INCORPORATING THE SAME
摘要 PURPOSE: A self-test circuit and memory device incorporating the same are provided to utilize a redundant cell and being suitable for relieving defective products. CONSTITUTION: The self-test circuit responds to an external test activating signal(WBIZ) and activated, generates a test operation command(WBI-CMD), generates a test address(WBI-ADD), and generates a test data(WBI-DATA). Also, after test data is written in a memory cell, the self-test circuit discriminates whether the data read out from the memory cell is same as the written test data or not, the comparison result is accumulated. And information of the comparison result is outputted to the outside.
申请公布号 KR20010067326(A) 申请公布日期 2001.07.12
申请号 KR20000060446 申请日期 2000.10.13
申请人 FUJITSU LIMITED 发明人 FUJIMOTO HIROYUKI;KANDA TATSUYA;MATSUZAKI YASUROU;NOMURA YUKIHIRO;SAITO MASAHIKO;SUZUKI TAKAHIRO;TOMITA HIROYOSHI
分类号 G01R31/28;G01R31/3185;G06F12/16;G11C11/401;G11C11/407;G11C29/06;G11C29/12;G11C29/44;(IPC1-7):G11C29/00 主分类号 G01R31/28
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