| 摘要 |
PURPOSE: An apparatus for diagnosing duplicated links is provided to simply confirm the abnormality of duplicated links in active and standby states. CONSTITUTION: An A-link abnormality detection apparatus is comprised of an abnormal mode setup circuit(120), a bit pattern generation circuit(130), a comparison circuit(140), and an interrupt generation circuit(150). The abnormal mode setup circuit(120) contains a mode register(121) and a timer(123). The timer(122) provides a cycle signal to the mode register(121). The mode register(121) provides an A-loop signal to a loop circuit when an interrupt bit and a selective bit are enabled. The bit pattern generation circuit(130) is composed of a bit pattern generator(131), a shift register(132) and a multiplexer(MUX11). The bit pattern generator(131) receives and stores a bit pattern provided from a CPU and provides it to the shift register(132). The shift register(132) provides the bit pattern to the multiplexer(MUX11) sequentially, corresponding to a transmitting clock(TxC). The multiplexer(MUX11) selectively outputs either the bit pattern of the shift register(132) or output data(TxD(A)) according to the control of the CPU. The comparison circuit(140) is composed of a multiplexer(MUX12), a shift register(141) and a comparator(142). The multiplexer(MUX12) selects the data provided from a link or the data provided from the multiplexer(MUX11) and provides the selected data to the shift register(141). The shift register(141) synchronizes the data of the multiplexer(MUX12) with a receiving clock(RxC) and supplies the data to the comparator(142). The comparator(142) compares the data of the shift register(141) and the data of the bit pattern generator(131) and provides a normal(or abnormal) indication signal to the interrupt generation circuit(150). The interrupt generation circuit(150) is comprised of a status register(151) and an interrupt request part(152). The status register(151) stores the normal(or abnormal) indication signal and provides the stored signal to the interrupt request part(152) and the CPU. The interrupt request part(152) supplies an interrupt signal to the CPU if the cycle signal from the timer(122) and the normal(or abnormal) indication signal from the status register(151) are supplied.
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