| 摘要 |
PURPOSE: A method for manufacturing a semiconductor memory device of a dual gate structure is provided to prevent a collecting phenomenon of a titanium salicide in a channeling phenomenon and a junction area of a poly-silicon layer in a dual gate structure which consists a stacked structure on which a poly-silicon layer and a titanium layer are deposited. CONSTITUTION: The method includes five steps. The first step is to sequentially form a gate oxide film(103) and a first poly-silicon layer on a semiconductor substrate(101), in which an active area(N) of an N-type and an active area(P) of a P-type are defined, and perform an ion implanting process to dope the first poly-silicon layer of the active area of the N-type with an N+ type. The second step is to form the second poly-silicon layer of P+ using an epitaxial growth method on the entire structure including the active areas of the N- and P-types. The third step is to etch the second poly-silicon layer, the first poly-silicon layer and the gate oxide film to form a gate pattern of NMOS and PMOS transistors on the active areas of the P- and N-types respectively. The fourth step is to perform an LDD ion implanting process, form a spacer on the both side walls of each of the gates of the NMOS and PMOS transistors and perform source and drain ion implanting process to form a junction area(B) of an LDD structure(A). The fifth step is to form a titanium salicide layer(108) on each gate of the NMOS and PMOS transistors with a salicide process using titanium.
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