| 摘要 |
PURPOSE: A rambus DRAM is provided to compensate for the leakage capacitor during transition from a power save mode to a normal operation mode in order to reduce setting time. CONSTITUTION: The rambus DRAM includes a memory core(100), a packet controller(200), a power mode controller(300) and a delay locked loop(500). The memory core incorporates a refresh counter. The packet controller analyzes a packet control signal applied from an external channel and generates an OP code signal controlling the power mode as well as the first control signal. The power mode controller generates a nap mode signal selecting the power save mode according to the first control signal, a power down mode signal, a doze mode signal and a self refresh enable signal controlling the refresh counter. The delay locked loop receives the nap mode signal, the power mode signal, the doze mode signal and the first clock signal and applies the second clock signal used inside of the memory device as well as the signal compensating and declaring the capacitor leakage during power save mode to the power mode controller.
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