发明名称 METHOD FOR FORMING SILICON WAFER FOR GOI EVALUATION
摘要 PURPOSE: A method for forming a silicon wafer for GOI(Gate Oxide Intefrity) evaluation is provided to check a GOI by performing a pre-thermal budget annealing process. CONSTITUTION: A thermal oxide layer(102) of 80-300 angstrom is formed on a silicon substrate(101). A pre-thermal budget annealing process(103) is performed. A post-thermal process is performed. The post-thermal process is performed continuously during 30 minutes under a temperature more than 1000 degrees centigrade. The previous oxide layer is removed. A gate oxide layer is grown as much as 50 to 500 angstrom. The first polysilicon used as an electrode is deposited on the gate oxide layer. A photoresist pattern is formed thereon. The first polysilicon layer and the gate oxide layer are removed from an opened region. An annealing process is performed.
申请公布号 KR20010065740(A) 申请公布日期 2001.07.11
申请号 KR19990065676 申请日期 1999.12.30
申请人 HYNIX SEMICONDUCTOR INC. 发明人 EUN, YONG SEOK;HONG, BYEONG SEOP;LEE, U YEONG
分类号 H01L21/66;(IPC1-7):H01L21/66 主分类号 H01L21/66
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