发明名称 Semiconductor memory device having redundancy circuit for relieving faulty memory cells
摘要 In a semiconductor memory device having a redundant cell array, a replacement control circuit stores in advance a faulty address in an address space assigned to the memory cell array and information for specifying the dimension of the faulty address, compares each of external addresses XA and YA with the stored faulty address, and detects their coincidence. When the external address coincides with the faulty address, a redundant row or a redundant column constituting the redundant cell array is selected and replaced with the faulty cell, on the basis of the information representing the dimension of the faulty address. By this operation, the faulty cell on the memory cell array can be flexibly relieved, and the flexibility of redundancy can be improved.
申请公布号 US6259636(B1) 申请公布日期 2001.07.10
申请号 US19990257505 申请日期 1999.02.25
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 FUKUDA RYO;NAMEKAWA TOSHIMASA
分类号 G11C11/401;G11C7/00;G11C29/00;G11C29/04;H01L21/8242;H01L27/108;(IPC1-7):G11C29/00 主分类号 G11C11/401
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