| 摘要 |
A static random access memory (SRAM) circuit includes four-transistor memory cells and is capable of high-speed reliable read operations. According to one embodiment, a SRAM circuit includes "n" memory cells (200-1 to 200-n) connected to digit line pairs (202-0 and 202-1). When selected, a memory cell (200-1 to 200-n) can draw an on current (Ion). When deselected, a memory cell (200-1 to 200-n) can draw a leakage current (Ioff) that can maintain a data value stored in a memory cell. High-speed and reliable operations may be achieved by meeting the following relationship:where K is 1 or more.
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