| 摘要 |
The memory cells at the very edge of an array are susceptible variations in transistor channel length and other attributes due to lithographic proximity effects. To reduce these undesirable edge effects, it is common to add non-functional sacrificial rows and columns of nearly identical memory cells around the periphery of a memory array. These "guard" cells (i.e., "end" cells, or "edge" cells) may provide, for at least the lower masking layers, a homogeneous lithographic environment at the edge of the functional array, but unfortunately consume area without adding to the storage capacity of the array. To save area, a group of functional memory cells in one array may also be used as guard cells for another memory array. The memory cells of the one array may, for example, be redundant memory cells serving the other memory array. In one embodiment having several memory submodules or banks, an array of four redundant rows is placed adjacent to the array of one of the memory banks. Separate sacrificial guard cells for the adjoining edge of the one memory bank are therefore no longer needed. Nonetheless, the lithographic environment at the edge of the regular array, for at least the lower masking layers, is homogeneous with the environment anywhere in the middle of the regular array. By abutting the redundant and normal memory cell arrays in this matter, the need for sacrificial guard cells for both arrays along their adjoining edges is eliminated, thus saving both layout area and layout complexity.
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