Method and apparatus for synchronizing data transfers in a logic circuit having plural clock domains

摘要

A synchronization circuit (30) includes three flip-flops responsive to a common clock signal (CLK2). The input to the first flip-flop (32) represents the least significant bit (LSB) of a counter (31) included within a first clock domain. The CLK2 signal originates from a second clock domain. The output of the first flip-flop is provided as input to the second flip-flop (34), and the second flip-flop output is provided as input to the third flip-flop (36). An exclusive-or (XOR) gate (38) generates a synchronization signal in response to outputs of the second and third flip-flops (34-36). The synchronization signal is usable within the second clock domain and activate for one period of CLK2 subsequent to every transition occurring on the LSB input. The active state of the synchronization signal indicates that a predefined set of data inputs is stable and valid. In this manner, a single unsynchronized input signal, i.e., the LSB input, can be used to synchronize the data inputs.