| 摘要 |
A novel method of forming a polysilicon gate tip (poly tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly tip is further enhanced by forming a notched nitride layer over the tip. At the same time, a method of forming a self-aligned source (SAS) line is disclosed. A relatively thin polygate is formed so as to decrease the growth of the protrusion of conventional gate bird's beak (GBB) to a smaller and sharper tip. It will be known by those skilled in the art that GBB is easily damaged during conventional poly etching where polyoxide is used as a hard mask. To use polyoxide as a hard mask, thick polysilicon is needed in the first place. Such thick poly will increase gate coupling ratio, which has the attendant effect of degrading program and erasing performance of the memory cell. Furthermore, as the cell size is being scaled down, poly oxidation is getting to be a difficult process due to oxide thinning effect, unless a protective measure is undertaken as disclosed in this invention. Finally, with the disclosed smaller poly tip of this invention in comparison with the GBB of prior art, the smaller is the encroachment under the polysilicon edge, and hence the smaller is the impact on the electric-field intensity between the corner edge of the floating gate and the control gate of the completed cell structure, and thus faster is the memory speed.
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