发明名称 System architecture for and method of processing packets and/or cells in a common switch
摘要 A novel networking architecture and technique for transmitting both cells and packets or frames across a common switch fabric, effected, at least in part, by utilizing a common set of algorithms for the forwarding engine (the ingress side) and a common set of algorithms for the QoS management (the egress part) that are provided for each I/O module to process packet/cell information without impacting the correct operation of ATM switching and without transforming packets into cells for transfer across the switch fabric.
申请公布号 US6259699(B1) 申请公布日期 2001.07.10
申请号 US19970001040 申请日期 1997.12.30
申请人 NEXABIT NETWORKS, LLC 发明人 OPALKA ZBIGNIEW;AGGARWAL VIJAY;KONG THOMAS;FIRTH CHRISTOPHER;COSTANTINO CARL
分类号 H04L12/56;H04Q11/04;(IPC1-7):H04L12/28 主分类号 H04L12/56
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