发明名称 |
Method and apparatus for controlling a synchronous memory device |
摘要 |
A method of controlling a synchronous memory device comprising issuing a write request to the memory device, wherein in response to the write request, the memory device samples first and second portions of data. The first portion of data is provided to the memory device synchronously with respect to a rising edge transition of an external clock signal. A second portion of data is provided to the memory device synchronously with respect to a falling edge transition of the external clock signal. A memory controller for controlling a synchronous memory device comprises output driver circuitry to output data. The output driver circuitry outputs a first portion of data in response to a rising edge transition of the first external clock signal. In addition, the output driver circuitry outputs a second portion of data in response to a falling edge transition of the first external clock signal.
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申请公布号 |
US6260097(B1) |
申请公布日期 |
2001.07.10 |
申请号 |
US20000514872 |
申请日期 |
2000.02.28 |
申请人 |
RAMBUS |
发明人 |
FARMWALD MICHAEL;HOROWITZ MARK |
分类号 |
G06F1/10;G06F11/00;G06F11/10;G06F12/00;G06F12/02;G06F12/06;G06F13/16;G06F13/376;G11C5/00;G11C5/06;G11C7/10;G11C7/22;G11C8/00;G11C11/401;G11C11/407;G11C11/4076;G11C11/409;G11C11/4096;G11C29/00;(IPC1-7):G06F13/00 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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