| 摘要 |
PROBLEM TO BE SOLVED: To provide an easy-to-fabricate flash EEPROM memory cell having a low erase write gate voltage. SOLUTION: An oxide tunneling layer 48, a polysilicon floating gate 52, a dielectric layer 56 and a control gate 60 are stacking on a substrate 40, and a trench is opened in an overlying interlayer insulation layer 94. A source junction part 90, a drain junction part 72 and an inclination pocket 78 of the opposite dope type are formed in the substrate 40 through ion implantation. The trench is filled with a metal layer 98 to complete a source electrode VS, a control gate VG and a drain electrode VD. Low positive biases are applied to the VD and VG, while a low negative bias is applied to Vsub and under a reverse biased state where the VS is floating, erase writing is performed by implanting net electrons into the floating gate 52 through back bias with a low potential applied to the control gate 60, thereby injecting hot holes.
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