| 摘要 |
<p>PROBLEM TO BE SOLVED: To simplify constitution of a row decoder circuit more than that of a conventional circuit. SOLUTION: An address signal is decoded by a decoder 51 including a NAND gate 52. A logic level of a decoded output is reversed depending on an erasion mode or other mode. After an address signal of a VCC group is decoded by the NAND gate 52 in the decoder 51, is converted in its level by two stages level shifters 56, 57, and supplied to a main decoder circuit. The level shifters 56, 57 are constituted of P channel transistors 61, 62 and N channel transistors 63, 64. Each source of the N channel transistors 61, 62 of the level shifter 56 is connected to a power source SWWL, and each source of the N channel transistors 63, 64 are connected to ground voltage VSS respectively. Each source of the N channel transistors 61, 62 of the level shifter 57 is connected to a power source SWWL, and each source of the N channel transistors 63, 64 are connected to a power source SBB resplactively.</p> |
