TIME FAULT SIMULATION METHOD

摘要

PROBLEM TO BE SOLVED: To provide a time fault simulation method by which whether or not a pertinent test pattern is provided with time fault inspection ability is verified for a time fault generated on a signal path inside a logic circuit for making signal change time fluctuate. SOLUTION: For the time fault generated on the signal path inside the logic circuit for making the signal change time fluctuate, prescribed timeΔt is defined as the time fault, the signal change time on the signal path is delayed for the prescribed timeΔt by the test pattern and circuit simulation is performed. Output signals from the logic circuit by the circuit simulation are compared with the output signal result of normal circuit simulation and when a difference between them is confirmed, it is defined that the time fault can be detected by the test pattern and it is defined that the time fault can not be detected by the test pattern when the difference can not be confirmed.