| 摘要 |
PROBLEM TO BE SOLVED: To provide a control circuit for reducing a dead cycle at the time of controlling the update of a TAG(tag) memory, and for improving access through-put at the time of updating the TAG memory. SOLUTION: This circuit for controlling the indexing and update of information for a tag memory 100 at the time of controlling a cache is provided with a tag update buffer 2 for buffering the update transaction of the tag memory 100, a tag index buffer 1 for buffering the indexing transaction of the tag memory 100, and an arbitration control circuit 3 having an address comparator for comparing the address of an update transaction in the tag update buffer 2 with the address of an indexing transaction in the tag index buffer 1 for controlling the arbitration of the update transaction in the tag update buffer 2 and the indexing transaction in the tag index buffer 1. When the coincidence of the addresses is detected by the comparator, the update transaction in the tag update buffer 2 is preferentially executed.
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