| 摘要 |
PROBLEM TO BE SOLVED: To provide a heterobipolar transistor, together with its manufacturing method, which has a low parasitic capacity and resistance, while enabling lowering of resistance of the internal base layer. SOLUTION: An Si substrate 150, a BOX layer 151, and a semiconductor layer 152 are laminated as an SOI structure. The semiconductor layer 152 is provided with a collector 101 of silicon, a SiGeC/Si layer 102 which surrounds the collector 101, an emitter 103 of n-type polysilicon, and an external base layer 104. The internal base layer 102a is constituted of an Si1-xGexCy layer. A heterojunction allows a lower resistance of the internal base layer, while the diffusion of impurity at the internal base layer comprising the Si1-xGexCy layer formed by epitaxial growth is suppressed.
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