| 摘要 |
A voltage stress testable embedded dual capacitor structure for use in an integrated circuit (IC). The voltage stress testable embedded dual capacitor structure includes a semiconductor substrate with an electrically insulating base layer thereon, a first embedded dual capacitor and a second embedded dual capacitor connected in series and disposed on the electrically insulating base layer, and a probe pad. The probe pad is electrically connected directly to the first and second embedded dual capacitors at a location therebetween (e.g. by being connected to an electrically conductive top plate of the second embedded dual capacitor). The voltage stress testable embedded dual capacitor structure can be voltage stress tested using an applied voltage high enough to assure the reliability of the first and second embedded dual capacitors, without exposing other electronic devices in the IC to a damaging level of voltage. Also provided is a process for voltage stress testing embedded dual capacitors. The process includes steps of first providing the voltage stress testable embedded dual capacitor structure described above, followed by voltage stress testing the first embedded dual capacitor. The voltage stress test step includes applying a first predetermined test probe voltage to the probe pad, thereby inducing a first predetermined electric field across the first embedded dual capacitor. The current flow across the first embedded capacitor resulting from that electric field is then measured. Subsequently, the second embedded dual capacitor is voltage stress tested in the same manner as the first embedded dual capacitor.
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