N-TIMES-OF-TWO CLOCK MULTIPLIER

摘要

PURPOSE: An N-times-of-two clock multiplier is provided which is able to multiply an input clock twice to N times of two and to be usefully used when various N-times-of-two clocks required for fast controlling a memory such as ROM/RAM having different operation speeds are simultaneously needed. CONSTITUTION: A clock multiplier includes N-stage N-times-of-two clock multipliers(10,20,30) for multiplying an input clock frequency supplied from the previous stage to generate multiplied clock frequencies, and a selector(50) for dividing L-bit control bits by the number of bits required for each multiplier to provide the bits to each multiplier. Each of the clock multipliers includes the first and second variable delay blocks for symmetrically delaying the input clock as many as required for each multiplier, and a logic operator for logically operating the outputs of the first and second variable delay blocks to generate the multiplied clock frequency of each multiplier.