| 摘要 |
PURPOSE: A method for manufacturing a metal interconnection of a semiconductor device is provided to remarkably decrease a dishing effect without an additional process for polishing an interlayer dielectric, by performing a planarization process before a two-step polishing processes, and by making target layers have the same polishing rate. CONSTITUTION: An interlayer dielectric(12) is formed on a semiconductor substrate(11) having a predetermined structure. A predetermined region of the interlayer dielectric is etched to expose a predetermined region of the semiconductor substrate. A barrier metal layer(13) and a copper thin film(14) are formed on the entire structure so that a step is formed between a cell region and a copper pad region. An insulation layer(15) is formed on the entire structure. The first chemical mechanical polishing(CMP) process is performed regarding the insulation layer and the copper thin film until the step between the cell region and the copper pad region is eliminated. The second CMP process is performed until the remaining insulation layer, the copper thin film and the barrier metal layer are eliminated and the interlayer dielectric is exposed.
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