| 摘要 |
PURPOSE: An output buffer circuit is provided to increase an access speed and to reduce an effect of noises by setting an output node to a predetermined voltage level, so reducing a peak current. CONSTITUTION: The output buffer circuit includes an output buffer(100), an output level detector(300), an output level adjuster(200) and an inverter(301). The output buffer(100) outputs an external input signal(sj) through an output node(dout2) in response to an output enable signal(poe). The output level detector(300) detects the voltage level of the output node when the output enable signal is disabled. The output level detector(300) operates only when reading data. The output level adjuster(200) pulls up/down the output node in response to a level detection signal(nod1) outputted from the output level detector(300) when the output enable signal is disabled. The inverters(301,112) invert the output enable signal.
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